Newisys is pleased to announce the release of Jove: The Open Verification Environment for the Java (TM) Platform. Jove is a set of Java APIs and tools to enable Verilog hardware design verification of ASICs and FPGAs using the Java programming language. It contains components that accomplish the following:

• Verilog simulator interaction (via PLI 2.0 aka VPI)
• Standalone behavioral simulation (i.e. a discrete event simulator)
• Thread and event synchronization
• Design Verification abstractions (e.g. clock-relative signal access, mailboxes, semaphores)
• Constraint-based randomization
• Dynamic Verilog shell generation

Jove has been tested extensively with Synopsys VCS and to a lesser extent with the GPL version of cver by Pragmatic C Software.

Information regarding the state of the project as well as the motivations behind it is available in the FAQ.

Binary and source code distributions are available at http://jove.sf.net/.

Jove is licensed under the Open Software License 2.0.

Java is a registered trademark of Sun Microsystems, Inc. in the U.S. or other countries.